The present invention relates to static timing analysis, and more specifically, to distributed timing analysis of a partitioned integrated circuit (IC) design.
Timing analysis is an important aspect of digital IC design or chip design. Timing analysis refers to analyzing the delay through each portion of the chip design to determine whether or not the timing requirements of the design are met. Timing analysis may be repeated at various stages of the design. A chip design is modeled as a timing graph with gate- and wire-pins denoted by timing nodes. Each connection from an input pin (source node) to an output pin (sink node) is denoted by a directed timing edge in the graph. Generally, timing analysis involves calculating delay through all the edges or paths between every chip source node and every chip sink node. The delay facilitates the determination of an arrival time of a signal to each node. Generally, arrival time at a given node is determined as a sum of the arrival time at the output of the previous node (i.e., at the input of the edge between the two nodes) and a delay through that edge. Arrival time at any node refers to the time at which the voltage at the node input reaches some part (e.g., half) of the maximum voltage value. Thus, another value of interest for each node is the slew, which indicates a transition rate of the voltage. A variety of known tests (e.g., setup test, hold test) may be implemented as part of the timing analysis.